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Debug Transport Module

Phase 1A: JTAG DTM


Spec Feature Coverage Summary

Spec Feature (Chapter)Vexriscv Debug ImplementationImplementation Details
Ch 6: Debug Transport Module (DTM)
JTAG TAP with IDCODE/dtmcs/dmi✅ ImplementedDebugTransportModuleJtag.scala — standard IR codes, dtmcs with version/abits/idle/dmistat, dmi with op/address/data
DMI bus protocol✅ ImplementedDebugInterfaces.scalaDebugBus with DebugCmd/DebugRsp, DebugBusSlaveFactory
DMI busy/error handling✅ Implementeddmihardreset, dmireset, pending/overrun detection
Cross-clock-domain DMI✅ ImplementedccToggle for JTAG↔debug clock domains
JTAG tunnel support✅ ImplementedJtagTunnel.scala — tunneling through outer TAP