System Integration — SWD

Goal is host-visible integration only (LiteX SoC, OpenOCD, GDB).

Note:

• Support for official RISC-V DM only (withPrivilegedDebug).
• One Debug transport per build — no JTAG-DTM + SWD-DTM on the same DebugBus without arbitration. Do not set JTAG_SIM=1 and SWD_SIM=1 together.

Code Repository :

• Litex - https://github.com/disdi/litex/tree/swd
• VexRiscv - https://github.com/disdi/VexRiscv/tree/phase3

(Update submodules in pythondata-cpu-vexriscv_smp to above branch)

SWD specific tasks

Step 1 (Already done)

• Create DebugTransportModuleSwd with io.swclk (input, probe-driven) + io.swdio as i/o/oe — Phase 2A–2C
• Add withSwdTransport() to DebugModuleFiber (mutually exclusive with withJtagTap() per build) — Phase 2C
• LiteX SMP cluster: swd param, --swd CLI, three-wire debugPort_swclk / swdio_{i,o,oe}, noTap guarded !jtagTap && !swd — Phase 3
• LiteX sim: --with-swd-debug, _Swd netlist token, add_swd(), swdremote on TCP 44854, SWD_SIM=1 Makefile targets — Phase 3
• OpenOCD smoke on sim: DPIDR 0x0ba11aab + dap apreg → dmstatus 0x004c0c82
• OpenOCD cfgs: openocd_swd_remote.cfg + vexriscv_swd.cfg (DAP + vexriscv_dmi_read/write + smoke)
• Cluster asserts: reject swd && jtagTap; require privilegedDebug when swd

Step 2 — host tooling + GDB (open)

• [~] Custom OpenOCD target: DAP/DMI procs done; riscv target glue + GDB still open
  • Exit: halt / resume / register read of the sim CPU over SWD (analogous to JTAG three-terminal)
  • Files: vexriscv_swd.cfg (extend), optional interface cfgs for hardware
  • Requires real hart in LiteX sim (not Phase2C stub DebugHartBus)
• Finalize DPIDR / AP_IDR before host scripts hard-code them
  • Rules + placeholders owned by Phase 2C (DPIDR=0x0BA11AAB, AP_IDR=0x74726976)
  • Must not look like ARM Cortex SW-DP (0x2ba01477 / DESIGNER 0x23B)
• GDB workflow on sim: target extended-remote :3333, set remotetimeout 120, monitor reset halt, info registers

JTAG — End to End Workflow

Official stack only (--with-privileged-debug + full JTAG TAP in sim) is already supported.

Prerequisites

• litex_sim
• OpenOCD
• riscv64-unknown-elf-gdb

Configs

Terminal 1 — sim (keep running)

litex_sim \
  --integrated-main-ram-size=0x10000 \
  --cpu-type=vexriscv_smp \
  --cpu-variant=linux \
  --cpu-count=1 \
  --with-privileged-debug \
  --jtag-tap \
  --with-jtagremote \
  --non-interactive

Wait for Found port 44853 and BIOS prompt litex>. First run may take several minutes (cluster regen + Verilator compile).

Terminal 2 — OpenOCD (after Terminal 1 is up)

openocd -f openocd_jtag_remote.cfg -f riscv_jtag_tunneled.tcl

Success indicators:

Info : JTAG tap: riscv.cpu tap/device found: 0x10003fff
Info : Examined RISC-V core; found 1 harts
Ready for Remote Connections
Info : Listening on port 3333 for gdb connections

Terminal 3 — GDB (after OpenOCD is ready)

riscv64-unknown-elf-gdb -ex "set remotetimeout 120" \
  -ex "set remote disable-packet-optimization 1" \
  -ex "target extended-remote localhost:3333" \
  demo/demo.elf

Load demo.elf (linked at 0x40000000) only after halt — this litex_sim invocation does not pass --ram-init=demo.bin, so the image is not preloaded:

monitor reset halt
load demo/demo.elf
break main
continue

SWD — what is possible now

step 1 landed LiteX + swdremote + OpenOCD smoke. In Terminal 3, NO GDB yet because vexriscv_swd.cfg deliberately does not target create riscv (stock OpenOCD has no RISC-V-over-SWD path).

Prerequisites (SWD-specific)

• litex_sim
• OpenOCD with SWD remote_bitbang
• GDB not usable on this path until step 2

Configs

Terminal 1 — sim (keep running)

litex_sim \
  --integrated-main-ram-size=0x10000 \
  --cpu-type=vexriscv_smp \
  --cpu-variant=linux \
  --cpu-count=1 \
  --with-privileged-debug \
  --with-swd-debug \
  --with-swdremote \
  --non-interactive

Wait for Found port 44854 and BIOS prompt litex>. First run may take several minutes (cluster regen + Verilator compile).

Do NOT pass --jtag-tap / --with-jtagremote here.

Terminal 2 — OpenOCD smoke (after Terminal 1 is up)

One-shot (connect, vexriscv_swd_smoke, exit):

openocd -s tcl \
  -f openocd_swd_remote.cfg \
  -f vexriscv_swd.cfg \
  -c init -c vexriscv_swd_smoke -c shutdown

Verified success:

Info : SWD DPIDR 0x0ba11aab
AP_IDR   = 0x74726976
dmstatus = 0x004c0c82 (version=2 authenticated=1 allrunning=1 allhalted=0)
PASS: SWD -> SW-DP -> DMI gateway -> DebugModule

Terminal 3 — GDB

Not supported yet (step 2).
No :3333 riscv GDB server from the SWD configs above.

when Step 2 is done — same shape as JTAG:

Host attach workflows (sim only)

Side-by-side