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Documentation

Phase 5: Documentation & Developer Interface

Done

  • Phase 2A–2C architecture chapters in this book (SwdPhy / SwdDp / SwdDmiGateway)
  • Operator how-to for sim three-terminal attach (JTAG and SWD) — Phase 3
  • Operator how-to for Arty hardware (JTAG via BSCANE2 USER4; SWD via MCU-Link CMSIS-DAP on Pmod JB) — Phase 3
  • Document placeholder DPIDR, AP_IDR, and Phase 2C DMI_ADDR / DMI_DATA / POSTED_READ map (see Phase 2C)
  • Published OpenOCD Vexriscv fork: disdi/openocd vexriscv-gateway (9786 + fixes + gateway; still unmerged upstream)

Still open

  • Broader user-facing guide beyond this stack (probe-rs, multi-probe notes)
  • Finalize published identification constants once IDs leave placeholder status
  • Document which optional RISC-V debug-spec features are implemented vs stubbed (dmstatus.version, abstract commands surface, triggers, SBA)